Testing And Verification (Dept Elec - III) (2181107)  

6
Credit
4 + 0 + 2
Lect + Tuto + Pract
Teaching Scheme
70 + 20 + 10
ESE + PA + ALA
Theory Marks
20 + 10 + 20
ESE + OEP + PA
Practical Marks
ESE - End Semester Examination, PA - Progress Assessment, ALA - Active Learning Assignments, OEP -Open Ended Problem


Rationale
This course provides a platform for students to understand importance of testing, fundamental VLSI test principles, basic concepts of design of testability (DFT), logic simulation and fault simulation, and various techniques for test pattern generation etc.
Course Outcome
1 To realize importance and challenges of VLSI Testing at different abstraction levels.
2 To study and apply various fault models for generation of test vectors.
3 To calculate observability and controllability parameters of given circuit.
4 To study techniques to improve testability of a given circuit.
5 To convert a given circuit into a scan design.
6 To apply concepts of logic simulation and fault simulation in designing and testing of VLSI circuits.
7 To identify the different characteristics of verification, and apply different verification methods.

Active Learning
Preparation of power-point slides, which include videos, animations, pictures, graphics for better understanding theory and practical work – The faculty will allocate chapters/ parts of chapters to groups of students so that the entire syllabus to be covered. The power-point slides should be put up on the web-site of the College/ Institute, along with the names of the students of the group, the name of the faculty, Department and College on the first slide. The best three works should submit to GTU.