Testing And Verification (Dept Elec - III) (2181107)  

List of Practicals

Sr. Practical Title
1
Write a VHDL/Verilog code to realize functioning of Observation Point Insertion technique.
2
Write a VHDL/Verilog code to realize functioning of control Point Insertion technique.
3
Write VHDL/Verilog code for MUX-D scan cell and Level Sensitive/edge triggered muxed-D scan cell
4
Write a VHDL/Verilog code to realize functioning of clocked scan cell and LSSD scan cell design
5
Write a VHDL/Verilog code to realize functioning of LSSD double latch design
6
Write a VHDL/Verilog code to realize functioning of Mixing negative-edge and positive-edge scan cell in a scan chain
7
Write a VHDL/Verilog code to realize functioning of Fixing bus contention in scan design rules
8
Write a VHDL/Verilog code to realize functioning of Adding a lock-up latch between crossclock-domain scan cells
9
To develop an exhaustive test bench for lower level combinational designs: 1. Adder and 2. multiplexer
10
To develop an exhaustive test bench for J-K flip-flop
11
To develop an exhaustive test bench for 4 bit up-down counter.
12
To verify an 8 bit shift register.
13
To prepare a complete test vector set for all possible stuck at faults parity checker where the data word is of 2 bit

Open Ended Problem
1 Write a C program to calculate observability and controllability parameters of given circuit.
2 Write a C program to generate test vectors for stuck at faults for a given combinational circuit.
3 Write a C program to generate test vectors for transistors faults for a given circuit.
Other
1. ngspice/xilinx (software)
2. www.nptel.ac.in
3. www.ocw.mit.edu
4. www.mosis.com
5. www.berkeley.edu