Testing And Verification (Dept Elec - III) (2181107)  

Syllabus

Sr. Topics Teaching Hours Module Weightage
1
Introduction:
Importance of Testing, Testing during VLSI Lifecycle, Challenges in VLSI Testing, Levels of Abstraction in VLSI Testing, Historical Review of VLSI Test Technology.
8
15 %
2
Design and Testability
Introduction, Testability Analysis, Design for Testability Basics, Scan Cell Designs, Scan Architectures, Scan Design Rules, Scan Design Flow, Special purpose Scan Designs, RTL Design for Testability
14
30 %
3
Logic and Fault Simulation:
Introduction, Simulation Models, Logic Simulation, Fault Simulation
10
20 %
4
Verification:
Importance of verification, Verification plan, Verification flow, Levels of verification, Verification methods and languages
8
15 %
5
Functional Verification
Introduction to test bench, Test bench architecture, Types of test benches, case study
12
20 %